Calibration circuit and memory device including the same

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United States of America Patent

PATENT NO 9805787
SERIAL NO

15334082

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A memory device may include a calibration circuit configured to perform a calibration operation of generating a pull-up control code and a pull-down control code in a calibration mode, and in a stress applying mode, turn on at least one of each of first and second transistor units to apply stress, and an on-die termination (ODT)/off-chip driver (OCD) circuit, a resistance value of the ODT/OCD circuit being adjusted in response to at least one of the pull-up control code and the pull-down control code. The calibration circuit includes a pull-up control code generator including the first transistor unit and a pull-down control code generator including the second transistor unit.

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Patent Owner(s)

  • SAMSUNG ELECTRONICS CO., LTD.

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ha, Kyung-soo Hwaseong-si, KR 36 178

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