Importance

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Abstract

An EPROM device includes bit lines branching from a supply voltage line, a first group of enablement signal lines intersecting the bit lines, unit cells respectively located at cross points of the bit lines and the first group of enablement signal lines, pass transistors, load transistors, comparators, and enablement signal generators. One of the pass transistors and one of the load transistors are coupled in series between the supply voltage line and each of the bit lines. Each of the comparators receives voltages of both ends of any one of the load transistors to generate an output signal. Each of the enablement signal generators receives one of the output signals of the comparators and one of a second group of enablement signals and outputs one of a third group of enablement signals to turn off one of the pass transistors responsive to a program current reaching a reference value.

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First Claim