Three-dimensional memory device with charge carrier injection wells for vertical channels and method of making and using thereof
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United States of America Patent
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Oct 31, 2017
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app pub date -
Aug 23, 2016
filing date -
Aug 23, 2016
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Abstract
A buried source semiconductor layer and p-doped semiconductor material portions are formed over a first portion of a substrate. The buried source semiconductor layer is an n-doped semiconductor material, and the p-doped semiconductor material portions are embedded within the buried source semiconductor layer. An alternating stack of insulating layers and spacer material layers is formed over the substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are formed as, or are replaced with, electrically conductive layers. The buried source semiconductor layer may be formed prior to, or after, formation of the alternating stack. The buried source semiconductor layer underlies the alternating stack and overlies the first portion of the substrate, and contacts at least one surface of the vertical semiconductor channels. The p-doped semiconductor material portions contact at least one surface of a respective subset of the vertical semiconductor channels.
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