Dual silicide liner flow for enabling low contact resistance
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United States of America Patent
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Oct 31, 2017
Issued Date -
N/A
app pub date -
Oct 30, 2015
filing date -
Oct 30, 2015
priority date (Note) -
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Abstract
A method for fabricating a semiconductor device includes depositing a sacrificial liner in self-aligned contact openings in first and second regions. The openings are filled with a sacrificial material. The second region is blocked with a first mask to remove the sacrificial material from the first region. The first mask is removed from the second region, and the sacrificial liner is removed from the first region. A first liner is formed in the openings of the first region, and first contacts are formed in the first region on the first liner. The first region is blocked with a second mask to remove the sacrificial material from the second region. The second mask is removed from the first region, and the sacrificial liner is removed from the second region. A second liner is formed in the openings of the second region, and second contacts are formed in the second region.
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