Method of packaging integrated circuits
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United States of America Patent
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Oct 31, 2017
Grant Date -
Jun 9, 2016
app pub date -
Feb 15, 2016
filing date -
Oct 1, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.
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