Semiconductor package including exposed connecting stubs
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United States of America Patent
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Oct 31, 2017
Grant Date -
Jul 28, 2016
app pub date -
Jan 20, 2016
filing date -
Jan 23, 2015
priority date (Note) -
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Abstract
A semiconductor package includes a substrate comprising a chip area and a peripheral area, at least one semiconductor chip mounted on the chip area, a plurality of stubs respectively on a plurality of pads arranged in the peripheral area, and a molding unit configured to cover at least a partial area of the at least one semiconductor chip and at least a partial area of the plurality of stubs on the substrate while exposing an upper surface of at least one of the plurality of stubs to outside of the molding unit, wherein at least a partial area of the upper surface of at least one of the plurality of stubs is substantially flat.
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