Semiconductor device layout, memory device layout, and method of manufacturing semiconductor device
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United States of America Patent
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Oct 31, 2017
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app pub date -
Jan 16, 2015
filing date -
Jan 16, 2015
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Abstract
A layout of a semiconductor device includes active area regions, gate electrodes crossing the plurality of active area regions, spacers along sides of the corresponding plurality of gate electrodes, a first contact patterning region, a second contact patterning region, and a contact area. The first contact patterning region overlaps at least one active area region among the plurality of active area regions, at least one gate electrode among the plurality of gate electrodes, and at least one spacer among the plurality of spacers, the at least one spacer corresponding to the at least one gate electrode. The second contact patterning region overlaps a portion of the first contact patterning region. The contact area overlaps the at least one active area region. A boundary of the contact area is defined by boundaries of the first contact patterning region, the second contact patterning region and the at least one spacer.
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