Through-memory-level via structures for a three-dimensional memory device
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United States of America Patent
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Oct 31, 2017
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N/A
app pub date -
Sep 19, 2016
filing date -
Dec 22, 2015
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Abstract
A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.
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