Controlling channel length for vertical FETs
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United States of America Patent
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Oct 31, 2017
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N/A
app pub date -
Feb 9, 2017
filing date -
Feb 9, 2017
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Abstract
A vertical-type semiconductor device includes a first source/drain (S/D) region on an upper surface of a semiconductor substrate. A channel region is on an upper surface of the first S/D region, and extends along the vertical axis to define a channel length. A second S/D region is on an upper surface of the channel region, and separates the second S/D region from directly contacting the semiconductor substrate. An electrically conductive gate wraps around all outer surfaces of the channel region. The gate extends along the vertical axis to define a gate length that is less than the channel length. Dielectric gate elements are interposed between an upper surface of the gate and a lower surface of the second S/D region, and are configured to electrically insulate the gate from the second S/D region.
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