System and method for synchronization among multiple PLL-based clock signals
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United States of America Patent
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Nov 7, 2017
Grant Date -
May 11, 2017
app pub date -
Jul 12, 2016
filing date -
Nov 11, 2015
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Abstract
A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common frequency reference signal and a common synchronization signal. Each PLL may have a reference signal frequency divider. The reference frequency divider may be phase-reset, for example, by a transition to a first logic state in the synchronization signal, and the output frequency dividers are each phase-reset, for example, by a transition to a second logic state following the transition to the first logic state in the synchronization signal. The transition to the first logic state may be, for example, a rising edge.
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