Circuit, method of using the circuit and memory macro including the circuit
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United States of America Patent
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Nov 7, 2017
Grant Date -
Dec 3, 2015
app pub date -
Aug 11, 2015
filing date -
Mar 15, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
A circuit includes a first latch for generating a first latched signal; and a first comparator for comparing the first latched signal and a write address, and generating a first comparator signal. The circuit includes a first logic circuit for receiving the first comparator signal and a fourth latched signal, and generating a first logic circuit output signal; and a second latch for receiving the first logic circuit output signal and generating a second latched signal. The circuit includes a third latch for generating a third latched signal; and a second comparator for comparing the third latched signal and a read address, and generating a second comparator signal. The circuit includes a second logic circuit for receiving the second comparator signal and the second latched signal, and generating a second logic circuit signal; and a fourth latch for receiving the second logic circuit signal and generating the fourth latched signal.
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