Nonvolatile memory device, storage device including nonvolatile memory device and operating method of nonvolatile memory device
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United States of America Patent
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Nov 7, 2017
Grant Date -
May 4, 2017
app pub date -
Nov 1, 2016
filing date -
Nov 2, 2015
priority date (Note) -
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Abstract
A nonvolatile memory device may include a memory cell array, an address decoder circuit, a page buffer circuit, and a control logic circuit. An erase operation includes iteratively performing an erase loop which includes an erase section where an erase voltage is applied to the memory cells of the selected memory block and an erase verification section where the memory cells of the selected memory block are verified using an erase verification voltage. If the memory cells of the selected memory block are determined as an erase pass in the erase verification section, the control logic circuit monitors the memory cells of the selected memory block. If the monitored result indicates that the memory cells of the selected memory block are at an abnormal state, the control logic circuit applies an extra erase voltage to the memory cells of the selected memory block.
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