Buffered multi-rank memory modules configured to selectively link rank control signals and methods of operating the same
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United States of America Patent
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Nov 7, 2017
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Jul 12, 2016
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Sep 25, 2015
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Abstract
A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.
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