Semiconductor device having compliant and crack-arresting interconnect structure
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United States of America Patent
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Nov 7, 2017
Issued Date -
N/A
app pub date -
Nov 15, 2016
filing date -
Feb 25, 2016
priority date (Note) -
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Abstract
A power converter (300) has a first transistor chip (310) conductively stacked on top of a second transistor chip (320) attached to a substrate (301). A first metallic clip (360) has a plate portion (360a) and a ridge portion (360c) bent at an angle from the plate portion. The plate portion is attached to the terminal of the first transistor chip opposite the second transistor chip. The ridge portion extends to the substrate is and is configured as a plurality of parallel straight fingers (360d). Each finger is discretely attached to the substrate using attachment material (361), for instance solder, and operable as a spring-line cantilever to accommodate, under a force lying in the plane of the substrate, elastic elongation based upon inherent material characteristics.
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