Vertically integrated wafers with thermal dissipation

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9812428
SERIAL NO

15299483

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Abstract

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Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.

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Patent Owner(s)

  • EMPIRE TECHNOLOGY DEVELOPMENT LLC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Luo, Zhijiong Poughkeepsie, US 255 4486

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