Interconnect structures for assembly of multi-layer semiconductor devices

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United States of America Patent

PATENT NO 9812429
SERIAL NO

15312063

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Abstract

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A multi-layer semiconductor device includes a first semiconductor structure having first and second opposing surfaces, the second surface of the first semiconductor structure having at least a first semiconductor package pitch. The multi-layer semiconductor device also includes a second semiconductor structure having first and second opposing surfaces, the first surface of the second semiconductor structure having a second semiconductor package pitch. The multi-layer semiconductor device additionally includes a third semiconductor structure having first and second opposing surfaces, the first surface of the third semiconductor structure having a third semiconductor package pitch which is different from at least the second semiconductor package pitch. The second and third semiconductor structures are provided on a same package level of the multi-layer semiconductor device. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

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Patent Owner(s)

  • MASSACHUSETTS INSTITUTE OF TECHNOLOGY

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Das, Rabindra N Lexington, US 53 1282
Gouker, Mark A Belmont, US 12 407
Gouker, Pascale Lexington, US 3 56
Johnson, Leonard M Carlisle, US 7 225
Johnson, Ryan C Woburn, US 5 92

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