Methods and systems for reducing electrical disturb effects between thyristor memory cells using buried metal cathode lines
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United States of America Patent
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Nov 7, 2017
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app pub date -
Jun 30, 2016
filing date -
Feb 8, 2016
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Abstract
Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.
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