Memory hole size variation in a 3D stacked memory
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United States of America Patent
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Nov 7, 2017
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N/A
app pub date -
Jun 7, 2016
filing date -
Jun 7, 2016
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Abstract
Techniques are provided for fabricating a memory device in which the memory cells have a uniform program and erase speed. In one aspect, a memory device is provided with memory holes having diameters which become progressively smaller as a distance between the memory holes and a local interconnect become progressively larger. In another aspect, a fabrication process is provided for such a memory device. The memory holes which are relatively closer to the local interconnect have a relatively thinner blocking oxide layer due to etching used to remove a sacrificial material of the control gate layers. The increased diameter compensates for the thinner blocking oxide layer.
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