PRECISE CONTROL OF VERTICAL TRANSISTOR GATE LENGTH
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United States of America Patent
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app pub date -
May 5, 2016
filing date -
May 5, 2016
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Abstract
Transistor and methods of forming the same include forming a channel fin on a bottom source/drain region. A dielectric fill is formed around the channel fin with a gap in an area directly above the channel fin that has a width greater than a width of the channel fin. Spacers are formed in the gap. The dielectric fill is etched away. A gate stack is formed on sidewalls of the channel fin directly underneath the spacers.
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