Backlight driver chip incorporating a phase lock loop (PLL) with programmable offset/delay and seamless operation
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United States of America Patent
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Nov 7, 2017
Grant Date -
Apr 30, 2015
app pub date -
Sep 30, 2014
filing date -
Oct 30, 2013
priority date (Note) -
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Abstract
The embodiments discussed herein relate to systems, methods, and apparatus for synchronizing a pulse width modulation (PWM) dimming clock signal with a frame rate signal, line sync signal, and/or a horizontal sync signal of a display device. The PWM dimming clock signal can be generated by a synchronization block having a programmable offset/delay. The programmable offset/delay can control the offset or phase difference between an input and an output clock signal of the synchronization block. Depending on the clock rate of PWM dimming and/or panel resolution, the phase/offset delay can be adjusted to achieve the optimum front of screen performance. Additionally, an input clock generator/missing pulse detection block can output a programmed clock signal to the synchronization block in case of a missing external clock, or insert a pulse when there is a missing pulse detected.
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