Wafer level integrated circuit contactor and method of construction
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 14, 2017
Issued Date -
N/A
app pub date -
Feb 15, 2016
filing date -
Apr 21, 2010
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). The elastomer is precompressed from its natural rest state between a top (22) plate and a bottom (70). Pre compression improves the resilient response of the pins. The pin crowns (40) are maintained relatively coplanar by the engagement of at least one flange (44a-b) against an up-stop surface 90 of plate 20, thereby insuring coplanarity of the crowns. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully