Memory device on-die error checking and correcting code

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United States of America Patent

PATENT NO 9817714
APP PUB NO 20170063394A1
SERIAL NO

14998142

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Abstract

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In a system where a memory device performs on-die ECC, the ECC operates on N-bit data words as two (N/2)-bit segments, with a code matrix having a corresponding N codes that can be operated on as a first portion of (N/2) codes and a second portion of (N/2) codes to compute first and second error checks for first and second (N/2)-bit segments of the data word, respectively. In the code matrix, a bitwise XOR of any two codes in the first portion of the code matrix or any two codes in the second portion of the code matrix results in a code that is either not in the code matrix or is in the other portion of the code matrix. Thus, a miscorrected double bit error in one portion causes a bit to be toggled in the other portion instead of creating a triple bit error.

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Patent Owner(s)

  • INTEL CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bains, Kuljit S Olympia, US 217 4685
Criss, Kjersten E Beaverton, US 10 108
Halbert, John B Beaverton, US 90 5334

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