Interconnect substrate having cavity for stackable semiconductor assembly, manufacturing method thereof and vertically stacked semiconductor assembly using the same
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United States of America Patent
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Nov 21, 2017
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N/A
app pub date -
Aug 25, 2016
filing date -
Sep 3, 2015
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Abstract
An interconnect substrate having vertical connection channels around a cavity is characterized in that contact pads are exposed from the cavity and the vertical connection channels are made of a combination of metal posts and metallized vias. The cavity includes a recess in a core layer and an aperture in a stiffener. The metal posts, disposed over the top surface of the core layer, are sealed in the stiffener and are electrically connected to a buildup circuitry adjacent to the bottom surface of the core layer. The minimal height of the metal posts needed for the vertical connection can be reduced by the amount equal to the depth of the recess. The buildup circuitry is electrically connected to the metal posts through the metallized vias and provides the contact pads exposed from the cavity for device connection.
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