Debug in a multicore architecture

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United States of America Patent

PATENT NO 9830241
SERIAL NO

14822667

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Abstract

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A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.

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Patent Owner(s)

Patent OwnerAddress
SYNOPSYS INC700 EAST MIDDLEFIELD ROAD MOUNTAIN VIEW CA 94043

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lippett, Mark David Watlington, GB 11 150
Oung, Ayewin Maidenhead, GB 5 49

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