Memory mapping in a processor having multiple programmable units
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United States of America Patent
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Nov 28, 2017
Grant Date -
Mar 10, 2016
app pub date -
Oct 14, 2015
filing date -
Dec 27, 1999
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Abstract
The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
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