Apparatus to reduce retention failure in complementary resistive memory

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United States of America Patent

PATENT NO 9830988
SERIAL NO

15187646

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Abstract

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Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; and a first transistor which is operable to cause a deterministic output on the first output node.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Augustine, Charles Portland, US 48 457
Lu, Shih-Lien L Portland, US 82 1689
Tomishima, Shigeki Portland, US 168 2927
Tschanz, James W Portland, US 93 1145
Wu, Wei Portland, US 1010 9430

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