Stress patterns to detect shorts in three dimensional non-volatile memory
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United States of America Patent
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Nov 28, 2017
Grant Date -
Nov 24, 2016
app pub date -
May 19, 2015
filing date -
May 19, 2015
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Abstract
A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns. The managing circuit applies one or more patterns of stress voltages to the vertical columns, with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts. The managing circuit tests for a short in the pairs of adjacent vertical columns after applying the one or more patterns of stress voltages. In one embodiment, the test may comprise programming a memory cell in each vertical column with data that matches the pattern of stress voltages, reading from the memory cells and determining whether data read matches data programmed. The applying of the stress voltages and the testing can be performed as part of a test during manufacturing or in the field during user operation.
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