Chip package and fabrication method thereof
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United States of America Patent
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Nov 28, 2017
Issued Date -
N/A
app pub date -
Apr 26, 2016
filing date -
Apr 28, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A chip package includes a chip, a laser stop layer, a first through hole, an isolation layer, a second through hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first through hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second through hole is extended from the third surface to the first surface, and the second through hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second through hole to contact the laser stop layer.
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