Staggered parity
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United States of America Patent
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Nov 28, 2017
Issued Date -
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app pub date -
Dec 14, 2016
filing date -
Dec 9, 2014
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Abstract
Forward Error Correction technique: parity vectors are computed such that each parity vector spans multiple FEC frames; in a given FEC frame, a first set of syndrome bits are due to the parity vectors, and a second set of syndrome bits satisfy FEC equations that involve bits of the given FEC frame including the first set of syndrome bits; and the parity vectors are staggered with respect to any sequence in which the FEC frames are processed. Values of decoded bits of a first frame are deduced from known bits of a first parity vector having an effective length of one frame. For parity vectors having an effective length greater than one frame, a Log Likelihood Ratio of each unknown bit associated with the first frame is updated based on known and unknown bits of each parity vector. First frame is decoded using deduced bit values and updated LLR values.
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Patent Owner(s)
- CIENA CORPORATION
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- [Patents Count]
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Harley, James | Nepean, CA | 48 | 820 |
Oveis, Gharan Shahab | Nepean, CA | 61 | 496 |
Roberts, Kim B | Ottawa, CA | 157 | 2930 |
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