Clock generation system with dynamic distribution bypass mode

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United States of America Patent

PATENT NO 9836078
SERIAL NO

15212044

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Abstract

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In some embodiments, a tight loop mode is provided in which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATIONSANTA CLARA CA

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Feldman, Allan Portland, US 12 106
Grossnickle, Vaughn Beaverton, US 6 31
Kurd, Nasser Portland, US 15 230
Mosalikanti, Praveen Portland, US 26 152
Neidengard, Mark Beaverton, US 9 61

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