Self-aligned gate last III-N transistors

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United States of America Patent

PATENT NO 9837499
SERIAL NO

15326022

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Techniques related to III-N transistors having self aligned gates, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a polarization layer between a raised source and a raised drain, a gate between the source and drain and over the polarization layer, and lateral epitaxial overgrowths over the source and drain and having and opening therebetween such that at least a portion of the gate adjacent to the polarization layer is aligned with the opening.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chau, Robert Beaverton, US 86 3295
Dasgupta, Sansaptak Hillsboro, US 243 1329
Gardner, Sanaz Hillsboro, US 23 93
Radosavlijevic, Marko Beaverton, US 3 9
Sung, Seung Hoon Portland, US 180 1333
Then, Han Wui Portland, US 300 1979

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