Mask design based on sensitivities to changes in pattern spacing
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United States of America Patent
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Dec 19, 2017
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app pub date -
Sep 15, 2016
filing date -
Feb 18, 2014
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Abstract
A layout of an integrated circuit design is provided and a plurality of multiple patterning decompositions is determined from the layout. Each decomposition of the plurality of multiple patterning decompositions includes patterns separated into masks. One or more files are generated that include sensitivities of pattern capacitances to changes in spacing between patterns due to mask shifts. Using the sensitivities and changes in spacing, respective worst-case performance values are determined for each decomposition. A mask set is selected based on the worst-case performance values.
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