Pattern weakness and strength detection and tracking during a semiconductor device fabrication process
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United States of America Patent
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Dec 19, 2017
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app pub date -
Mar 10, 2016
filing date -
Apr 13, 2015
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Abstract
Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.
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