Method and apparatus for performing reduction operations on a set of vector elements
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United States of America Patent
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Dec 26, 2017
Grant Date -
Jun 23, 2016
app pub date -
Dec 23, 2014
filing date -
Dec 23, 2014
priority date (Note) -
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Abstract
An apparatus and method are described for performing SIMD reduction operations. For example, one embodiment of a processor comprises: a value vector register containing a plurality of data element values to be reduced; an index vector register to store a plurality of index values indicating which values in the value vector register are associated with one another; single instruction multiple data (SIMD) reduction logic to perform reduction operations on the data element values within the value vector register by combining data element values from the value vector register which are associated with one another as indicated by the index values in the index vector register; and an accumulation vector register to store results of the reduction operations generated by the SIMD reduction logic.
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