Split-level history buffer in a computer processing unit
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United States of America Patent
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Dec 26, 2017
Issued Date -
N/A
app pub date -
Sep 16, 2016
filing date -
Jun 16, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A split level history buffer in a central processing unit is provided. A first instruction and a second instruction are fetched, tagged, and the first instruction is stored an entry of a register file. The first instruction is evicted from the entry and the second instruction is stored in the entry. If the first instruction is evicted, then the first instruction is stored in a first portion of a history buffer. If a result for the first instruction is generated, then the first instruction is moved to a second portion of the history buffer and the result is stored with the first instruction in the second portion of the history buffer. If it is determined that a third instruction evicts the second instruction from the entry, then the second instruction is stored in the first portion of the history buffer.
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