Non-volatile multi-level-cell memory with decoupled bits for higher performance and energy efficiency
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United States of America Patent
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Dec 26, 2017
Grant Date -
Dec 17, 2015
app pub date -
Jan 31, 2013
filing date -
Jan 31, 2013
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Abstract
A non-volatile multi-level cell (“MLC”) memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write latencies and energies.
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