Chip scale sensing chip package
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United States of America Patent
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Dec 26, 2017
Issued Date -
N/A
app pub date -
Jan 19, 2017
filing date -
Jan 27, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
This present invention provides a chip scale sensing chip package, comprising: a sensing chip with a first top surface and a first bottom surface opposite to each other, comprising: a sensing device adjacent to the first top surface; and a plurality of conductive pads adjacent to first top surface and the sensing device; a wiring layer formed on the first bottom surface and connected to each of the conductive pads; a dam having a supporter with a first opening and a spacer with a second opening formed on the first top surface, wherein the supporter is within the second opening and adjacent to the spacer, and the spacer is higher than the supporter by a predetermined distance d; a lens formed on the first top surface exposed by the first opening and above the sensing device; and an optical filter deposed on the supporter and above the lens.
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