Fully silicided linerless middle-of-line (MOL) contact
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United States of America Patent
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Dec 26, 2017
Issued Date -
N/A
app pub date -
Sep 17, 2015
filing date -
Sep 17, 2015
priority date (Note) -
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Abstract
A method of making a semiconductor device includes forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack including a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the first layer of silicon material; and performing a silicidation process to form a source/drain contact including a silicide.
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