Phase domain calculator clock, ALU, memory, register file, sequencer, latches

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United States of America Patent

PATENT NO 9853649
SERIAL NO

15269245

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Abstract

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A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

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Patent Owner(s)

  • TEXAS INSTRUMENTS INCORPORATED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Shi, Fuqiang Oak Park, US 45 683
Staszewski, Robert B Garland, US 116 3550
Staszewski, Roman McKinney, US 12 398

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