Method for manufacturing dual damascene structure

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United States of America Patent

PATENT NO 9859150
SERIAL NO

15207189

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Abstract

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A method for manufacturing a semiconductor device include forming a dielectric layer over an underlying layer; forming an etch barrier over the dielectric layer, wherein a partial via opening is formed in the etch barrier and exposes a lower portion of the etch barrier; forming an assist-etch barrier over the etch barrier to fill the partial via opening; patterning the assist-etch barrier to form an initial trench opening in the assist-etch barrier, wherein the initial trench opening communicates with the partial via opening; patterning the lower portion of the etch barrier exposed by the partial via opening to form a final via opening in the etch barrier; patterning the dielectric layer exposed by the final via opening to form an initial via hole in the dielectric layer; patterning the etch barrier exposed by the initial trench opening to form a final trench opening in the etch barrier; patterning a lower portion of the dielectric layer exposed by the initial via hole to form a final via hole in the dielectric layer; and patterning a upper portion of the dielectric layer exposed by the final trench opening to form a trench, wherein the trench communicates the final via hole.

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Patent Owner(s)

  • SK HYNIX INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jung, Jin-Gi Gyeonggi-do, KR 1 2

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