Chip package and manufacturing method thereof
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United States of America Patent
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Jan 2, 2018
Issued Date -
N/A
app pub date -
Dec 28, 2016
filing date -
Dec 29, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A chip package includes a chip, an insulating layer and a conductive layer. The chip includes a substrate, an epitaxy layer, a device region and a conductive pad. The epitaxy layer is disposed on the substrate, and the device region and the conductive pad are disposed on the epitaxy layer. The conductive pad is at a side of the device region and connected to the device region. The conductive pad protrudes out of a side surface of the epitaxy layer. The insulating layer is disposed below the substrate and extended to cover the side surface of the epitaxy layer. The conductive layer is disposed below the insulating layer and extended to contact the conductive pad. The conductive layer and the side surface of the epitaxy layer are separated by a first distance.
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