Node isolation for protection from electrostatic discharge (ESD) damage

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United States of America Patent

PATENT NO 9859704
SERIAL NO

15417656

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Abstract

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An embodiment includes a tie-off circuit includes multiple field effect transistors (FETs), and a node isolation circuit that is connected to a first output node and a second output node of the tie-off circuit. The node isolation circuit consists of a first FET with a third output node and a second FET with a fourth output node. The second output node includes a logical LO node and is coupled to a gate of the first FET and generates a TIE HI output.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Guo, Chen San Jose, US 28 52
Nakamura, Yutaka Kyoto, JP 199 2437
Sawada, Jun Austin, US 86 625

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