Standard cell architecture for reduced parasitic resistance and improved datapath speed

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United States of America Patent

PATENT NO 9859891
SERIAL NO

15192872

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Abstract

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A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a Mx layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the Mx layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a My layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the My layer that is coupled to the second output on the fifth track.

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Patent Owner(s)

  • QUALCOMM INCORPORATED

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Guttal, Radhika Vinayak San Diego, US 3 16
Kumar, Dorav San Diego, US 10 49
Narayanan, Venkatasubramanian San Diego, US 20 66
Paturi, Sivakumar San Diego, US 1 1
Rasouli, Seid Hadi San Diego, US 22 106
Thalla, Bala Krishna San Diego, US 1 1

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