Buffer with programmable input/output phase relationship
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United States of America Patent
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Jan 2, 2018
Issued Date -
N/A
app pub date -
Mar 8, 2016
filing date -
Mar 8, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
An apparatus includes a phase locked loop circuit having a phase comparator for generating a signal indicative of a phase difference between a signal presented to a first input of the phase comparator and a signal presented to a second input of the phase comparator. The apparatus includes at least one delay element disposed so as to enable contributing at least one of the following:
- i) delay to a signal provided to the first input of the phase comparator;ii) delay to a signal provided to the second input of the phase comparator.A delay contributed by the at least one delay element varies in accordance with an associated delay control value. The phase locked loop circuit and the at least one delay element reside on a same semiconductor substrate.
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