Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memory

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United States of America Patent

PATENT NO 9865322
SERIAL NO

15280935

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Abstract

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Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dray, Cyrille Hillsboro, US 37 234
Hamzaoglu, Fatih Portland, US 48 338
Lin, Blake C Portland, US 9 39
Wang, Yih Portland, US 237 699
Wei, Liqiong Portland, US 19 155

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