Chip package and method for forming the same

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9865526
SERIAL NO

14877806

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A chip package including a first substrate having an upper surface, a lower surface and a sidewall is provided. A sensing region or device region and a conducting pad are adjacent to the upper surface. A through-hole penetrates the first substrate. A redistribution layer extends from the lower surface into the through-hole and is electrically connected to the conducting pad. The redistribution layer further laterally extends from the lower surface to protrude from the sidewall. A method for forming the chip package is also provided.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
XINTEC INC9F NO 23 JILIN RD ZHONGLI DIST TAOYUAN CITY 320

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Huang, Yu-Lung Taoyuan, TW 46 204

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
7.5 Year Payment $3600.00 $1800.00 $900.00 Jul 9, 2025
11.5 Year Payment $7400.00 $3700.00 $1850.00 Jul 9, 2029
Fee Large entity fee small entity fee micro entity fee
Surcharge - 7.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00