Fault current reduction structure of multi-level converter and apparatus using the fault current reduction structure
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United States of America Patent
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Jan 16, 2018
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app pub date -
Jul 10, 2015
filing date -
Jul 10, 2014
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Abstract
Provided are a multi-level converter having more than one converter arm in which a plurality of sub-modules are connected in series, multi-level converter comprising, a first bypass circuit connected in parallel to at least one sub-module included in more than one converter arm on a first side and including a first switching device, a second bypass circuit connected in parallel to more than one converter arm on a second side and including a diode, a second switching device included in more than one converter arm and having a first end connected in series to at least one sub-module and a second end connected to a first end of first bypass circuit at a single node and a third switching device included in more than one converter arm and having a first end connected in series to at least one sub-module and a second end connected to a first end of second bypass circuit at a single node.
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