Chip package and manufacturing method thereof
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United States of America Patent
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Jan 23, 2018
Issued Date -
N/A
app pub date -
Nov 21, 2016
filing date -
Nov 23, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.
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