Methods and apparatus for clock gating processing modules based on hierarchy and workload

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United States of America Patent

PATENT NO 9880603
SERIAL NO

13799234

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Abstract

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A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to a first processing module and a second processing module. The first processing module has a priority higher than a priority of the second processing module. The dispatch module includes a workload counter associated with the first processing module to provide an indication of a workload at the first processing module. The dispatch module initiates a clock signal at the second processing module only if the indication of the workload at the first processing module satisfies a criterion. The dispatch module sends a data unit to the second processing module for processing only if the indication of the workload at the first processing module satisfies a criterion.

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Patent Owner(s)

  • JUNIPER NETWORKS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kulkarni, Vaishali San Jose, US 10 23
Libby, Jeffrey G Cupertino, US 42 402
Ofelt, David J Menlo Park, US 16 185

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