Suppression of program disturb with bit line and select gate voltage regulation
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United States of America Patent
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Jan 30, 2018
Issued Date -
N/A
app pub date -
Apr 25, 2017
filing date -
Dec 13, 2016
priority date (Note) -
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Abstract
Techniques for suppression of program disturb in memory devices are described herein. In an example embodiment, a memory device comprises a flash memory array coupled to a control circuit. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). The control circuit is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory array, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the memory device.
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